1. Field of the Invention
The present invention generally relates to integrated circuit and flat panel display fabrication. More specifically, the invention relates to process sequences for fabricating copper interconnect structures and other metallization structures.
2. Background of the Related Art
Modern semiconductor integrated circuits usually involve multiple metal layers separated by dielectric (insulating) layers, such as silicon dioxide or silica, often referred to simply as an oxide layer, although other materials are being considered for use as the dielectric. The layers are electrically connected by interconnects (i.e., lines, vias and contacts) which penetrate the intervening oxide layer and contact some underlying conductive feature.
Interconnects have presented an increasingly difficult problem as integrated circuits are formed with an increasing density of circuit elements because the feature sizes have continued to shrink. For logic applications, the thickness of the oxide layer seems to be constrained to the neighborhood of 1 xcexcm, while the diameter of contacts and vias is being reduced from the neighborhood of 0.35 xcexcm to 0.18 xcexcm and below. As a result, the aspect ratios (the ratio of the depth to the minimum lateral dimension) of the contacts and vias are being pushed to 5:1 and above.
As sizes continue to decrease, the characteristics of the material forming the interconnects become increasingly important. The smaller the feature, the less resistive the material forming the feature should be for speed performance. Copper is a material which is becoming more important as a result. Copper has a resistivity of 1.7 xcexcxcexa9.cm and a small RC time constant thereby increasing the-speed of a device formed thereof. In addition, copper exhibits improved reliability over aluminum in that copper has excellent electromigration resistance and can drive more current in the lines.
One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials. Therefore, conformal barrier layers become increasingly important to prevent copper from diffusing into the dielectric and compromising the integrity of the device. Barrier layers for copper applications are available for interlayer dielectric applications. The use of a thin silicon nitride (SiN) layer on the interlayer dielectric will effectively inhibit interlayer diffusion. Within the same dielectric layer it is difficult to provide an effective barrier to prevent leakage between lines. Several technologies are presently under investigation which add a barrier liner to the via sidewall separating the copper metal from the interlayer dielectric. Common physical vapor deposition (PVD) technologies are limited in high aspect ratio and re-entrant structures due to the directional nature of their deposition. The barrier thickness will depend directly upon the structure architecture with the barrier becoming thinner on the sidewall near the structure bottom. The barrier thickness, and therefore the barrier integrity, will be compromised under overhangs on re-entrant structures.
In contrast, CVD deposited films are by their nature conformal in re-entrant structures. Further, CVD deposited films maintain a high degree of conformity to the structure""s lower interface. Silicon nitride (SixNy) and titanium nitride (TiN) prepared by decomposition of an organic material (TDMAT) are common semiconductor manufacturing materials which display the described conformal performance. Both materials are perceived as being good barriers to Cu interdiffusion, but are considered unattractive due to their high resistivity. The high resistive nature of the material would detrimentally affect the via resistance performance which must be maintained as low as possible to maximize device performance.
Therefore, there is a need for a process sequence and related hardware which provides a good barrier layer on the aperture sidewall, but which does not negatively affect the resistance of the plug.
The invention generally provides process sequences for depositing copper interconnects and other metallization features. In one embodiment, a patterned substrate having a contact, via, line or other conductive feature thereon, is introduced into a first chamber where a barrier layer comprising tantalum, tantalum nitride, SixNy or other suitable barrier layer is formed thereon. The substrate is preferably cleaned prior to deposition of the barrier layer to remove native oxides or other contaminants from the substrate. The barrier layer is preferably deposited to a thickness of about 200 to about 500 xc3x85 using a high density plasma physical vapor deposition chamber. Following deposition of the barrier layer, a copper or other metal film is deposited on the barrier layer. Preferably, copper is first deposited using a high density plasma physical vapor deposition technique followed by 1) electroplating, 2) physical vapor deposition copper reflow, 3) chemical vapor deposition followed by physical vapor deposition copper reflow, or 4) chemical vapor deposition.